A circuit widely used in analog systems for amplifying signals superimposed on a variable continuous component reaching voltage levels close to the supply lines is a rail-to-rail operational amplifier. When it is no longer possible to use a common output stage, more complex circuit approaches become necessary. The amplifier must be able to handle an input signal having an amplitude equal to the voltage difference between the two supply rails, while providing an output signal having an amplitude that may equal such a voltage difference. There is a wealth of approaches described in the prior art which address certain known problems, but nonetheless, these approaches often have well-recognized drawbacks.
To better illustrate an approach for these known problems, and the advantages provided by the circuit of the invention, it is useful to refer to a circuit described in the IEEE Journal of Solid State Circuits, vol. 29, No. 12, December 1994, wherein a rail-to-rail amplifier for VLSI cells is disclosed. FIG. 1 shows an output stage in which the current generators may be formed with MOS transistors. The minimum supply voltage is equal to : EQU Vsuppmin=2*Vgs(pch.vertline.nch)+Vds(sat)
By using 1 .mu.m BiCMOS technology with voltage thresholds of 0.64V for the N-channel, and -0.75V for the P-channel, the minimum supply voltage will be Vsuppmin=2V. The maximum voltage determined by such a low voltage fabrication technology is 6V.
The lin1 and lin2 lines originate from the input stage, which is not shown in the figure because it is not essential for the following discussion. The two signal currents provided by lines lin1 and lin2 must be in phase with each other. If we assume that the signal current is flowing in, the current available to the complementary pair of control MOS transistors M4 and M5 will be increased on the high side transistor because of line lin1. For the low side transistor, the current is decreased because a portion is input along line lin2 by the input stage.
This condition induces a shift towards a higher potential for the pair of control MOS transistors for the class AB stage transistors M4 and M5. As the voltage at the source of transistor M5 increases while the voltage on its gate remains constant, the current flowing in transistor M5 decreases while the current flowing in transistor M4 increases. The gate voltage of transistor M4 remains constant while its source voltage increases. This causes a voltage increase on the gates at the output of MOS transistors M3 and M6.
Input currents lin1 and lin2 are the bias current generated by the respective I1 and I3 current generators. If the input currents lin1 and lin2 become equal, the current through the control transistors M4 and M5 become null and the gate voltages of transistors M3 and M6 will be different only by a saturation Vds voltage of the transistor M4. In this case, transistor M6 is turned on at the maximum possible Vgs voltage, which is given by: EQU Vgs(max)=Vdd-2*Vds(sat)
M5 is turned off at the lowest possible Vgs voltage, which is given by: EQU Vgs(min)=Vds(sat)
This condition is also duplicated when the two signal currents on lines lin1 and lin2 are flowing out of the output stage. Hence, the two turn on voltages Vds(sat) for both the output MOS transistors M3 and M6 are nearly saturated. Such a voltage could become very useful when the supply voltage decreases, i.e., in applications intended to function at relatively low voltages.